Processor processing method

Abstract

PURPOSE: To surely carry out the interruption processing even under execution of a branch instruction by saving the address information on the instructions of a cycle and its following one and then carrying out the address information when the interruption processing is over when an interruption request is received during a series of operation cycles. CONSTITUTION: In a pipeline control system where a program storing part 1 is connected to a sequencer 2 via an independent instruction information bus 9, the sequencer 2 saves the both address information on an instruction fetched in a cycle where an interruption request is received during the execution of a series of operation cycles and on the instruction fetched in the following cycle. Then the instruction information designated by both address information are fetched and executed when the interruption processing carried out by an interruption request is over. Thus the interruption processing can be surely carried out at a high speed. COPYRIGHT: (C)1992,JPO&Japio

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